1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuit layout, and more specifically to the art of routing nets on integrated circuit chips.
2. Description of Related Art
Microelectronic integrated circuits consist of a large number of electronic components which are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in the various layers of the silicon chip.
The process of converting the specifications of an electrical circuit into a layout is called physical design. Physical design requires arranging elements, wires, and predefined cells on a fixed area, and the process can be tedious, time consuming, and prone to many errors due to tight tolerance requirements and the minuteness of the individual components, or cells.
Currently, the minimum geometric feature size of a component is on the order of 0.5 microns. Feature size may be reduced to 0.1 micron within the next several years. The current small feature size allows fabrication of as many as 10 million transistors or approximately 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This feature-size-decrease/transistor-increase trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit. Larger chip sizes will allow far greater numbers of circuit elements.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design use extensively Computer Aided Design (CAD) tools. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
The object of physical chip design is to determine an optimal arrangement of devices in a plane and to find an efficient interconnection or routing scheme between the devices that results in the desired functionality. Since space on the chip surface is at a premium, algorithms must use the space very efficiently to lower costs and improve yield. The arrangement of individual cells in an integrated circuit chip is known as a cell placement. In the following description, each arrangement of cells will be referred to as a placement.
Each microelectronic circuit device or cell includes a plurality of pins or terminals, each of which is connected to pins of other cells by a respective electrical interconnection wire network, or net. A purpose of the optimization process used in the physical design stage is to determine a cell placement such that all of the required interconnections can be made, but total wirelength and interconnection congestion are minimized. The process of determining the interconnections of already placed cells of an integrated circuit is called routing.
Assuming that a number N of cells are to be optimally arranged and routed on an integrated circuit chip, the number of different ways that the cells can be arranged on the chip, or the number of permutations, is equal to N| (N factorial). In addition, each of the cells may require multiple connection points (or pins), each of which, in turn, may require connections to multiple pins of multiple cells. The possible routing permutations are even larger than the possible cell placements by many orders of magnitude.
Because of the large number of possible placements and routing permutations, even computerized implementation of the placement algorithms discussed above can take many days. In addition, the placement and routing algorithms may need to be repeated with different parameters or different initial arrangements to improve the results.
To reduce the time required to optimally route the nets, multiple processors have been used to speed up the process. In such implementations, multiple processors are assigned to different areas of the chip to simultaneously route the nets in its assigned areas. However, it has been difficult to evenly distribute the amount of routing required from each of the multiple processors. In fact, due to the nonlinear algorithm complexity, the obvious, always assumed parallelization which is to split the nets among the processors does not work because routing of one highest fanout net can take much longer than routing of all other nets of the integrated circuit. Such unbalanced parallelization of the routing function has been the norm in the art, leading to ineffective use of parallel processing power.
In summary, because of the ever-increasing number of cells on an integrated chips (currently at millions of cells on a chip), and the resulting increase in the number of possible routing of the cells and the nets on the chips, multiple processors are used to simultaneously route the nets of an integrated chip. However, even with the aid of computers, existing methods can take several days, and the addition of processors may not decrease the required time because of the difficulties of balancing the amount of work between the processors.